Umesh Prasad's repositories
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
C
Collection of various algorithms in mathematics, machine learning, computer science, physics, etc implemented in C for educational purposes.
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
cocotb-bus
Pre-packaged testbenching tools and reusable bus interfaces for cocotb
cocotb-test
Unit testing for cocotb
cocotbext-eth
Ethernet interface modules for Cocotb
dpll
A collection of phase locked loop (PLL) related projects
generative-ai-for-beginners
18 Lessons, Get Started Building with Generative AI đź”— https://microsoft.github.io/generative-ai-for-beginners/
interpolation
Digital Interpolation Techniques Applied to Digital Signal Processing
iob-cache
Verilog configurable cache
kianRiscV
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
malwoverview
Malwoverview is a first response tool used for threat hunting and offers intel information from Virus Total, Hybrid Analysis, URLHaus, Polyswarm, Malshare, Alien Vault, Malpedia, Malware Bazaar, ThreatFox, Triage, InQuest and it is able to scan Android devices against VT.
markdown2congluence
Sync markdown files with Confluence pages.
PeakRDL
Control and status register code generator toolchain
pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
pyxsi
Python/C/RTL cosimulation with Xilinx's xsim simulator
rggen
Code generation tool for configuration and status registers(todo)
sdspi
SD-Card controller, using a SPI interface that is (optionally) shared
style-guides
lowRISC Style Guides
switchboard_VE
Communication framework for RTL simulation and emulation.
telegram-get-remote-ip
Get IP address on other side audio call in Telegram.
tvip-axi
AMBA AXI VIP
umi
Universal Memory Interface (UMI)
VeeRwolf
FuseSoC-based SoC for SweRV EH1 and EL2
verilog-pcie
Verilog PCI express components
wal
WAL enables programmable waveform analysis.