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Prajwal D Nayak (prajwal0718)

prajwal0718

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Prajwal D Nayak's repositories

Synchronous-FIFO

Verilog and systemverilog projects

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Asynchronous-FIFO

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FIFO_Layered_TB

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Functional-Coverage

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Layerd-TestBench-Full-Adder

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Processor

Simple Processor is created in verilog and tested

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