Anthony Campos's repositories
async_FIFO
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
Language:SystemVerilogMIT000
axi4-interface
AXI4 and AXI4-Lite interface definitions
Language:SystemVerilogGPL-3.0000
easyUVM
A simple UVM example with DPI
Language:SystemVerilogMIT000
Gaia
Generate UVM testbench framework template files with Python 3
Language:SystemVerilogApache-2.0000
logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Language:SystemVerilogApache-2.0000
pulse-compression-filter-on-an-FPGA
The Design and Implementation of a Pulse Compression Filter on an FPGA.
Language:VerilogUnlicense000
rggen
Code generation tool for configuration and status registers
Language:RubyMIT000
Simple_UVM
Implements a simple UVM based testbench for a simple memory DUT.
Language:SystemVerilogMIT000
tvip-axi
AMBA AXI VIP
Language:SystemVerilogApache-2.0000
uvm_gen
UVM Generator
Language:SystemVerilogApache-2.0000
UVM_UART_Example
An UVM example of UART
Language:SystemVerilog000