phamquanganhBKSET / risc_v

RISC-V 5 stages pipeline IF, ID, EX, MEM, WB with forwarding, stalling and branch prediction

This repository is not active

RISC-V 5 stages pipeline IF, ID, EX, MEM, WB with forwarding, stalling and branch prediction

Language:Verilog 60.0%Language:Stata 34.8%Language:SystemVerilog 2.7%Language:Assembly 1.6%Language:Python 0.9%