Giters
peteut
/
migen-axi
AXI support for Migen/MiSoC
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Stargazers:
23
Watchers:
10
Issues:
17
Forks:
14
peteut/migen-axi Issues
Unbreak build and CI
Closed
a year ago
I would like use it with PYNQ board
Updated
4 years ago
Comments count
1
Migen platform compatibility
Closed
4 years ago
Comments count
1
compatibility with new MiSoC identifier core
Closed
4 years ago
typo in soc_core.py
Closed
5 years ago
Channels Should be Stream Interfaces
Updated
5 years ago
High-Speed DMA Controller Peripheral
Updated
6 years ago
misoc.interconnect.stream -> DMAC | PRI
Closed
6 years ago
Comments count
4
Add Documentation
Updated
6 years ago
Expose `dma[:].rst_n` from `PS7`
Closed
6 years ago
Consider rename from migen-formal to migen-axi or migen-zynq
Closed
6 years ago
Comments count
3
Is anyone working on this project a Uni student?
Updated
6 years ago
Comments count
2
Add AXI4-Lite Bridge Module
Updated
6 years ago
Comments count
2
AXI2CSR W/ 16 Bits Bus
Closed
6 years ago
Comments count
1
CSR Shall Be Word Aligned
Closed
6 years ago
DT Overlay Generator
Updated
6 years ago
Comments count
3
Tests for AXI2CSR
Closed
6 years ago