palindali / SoC-Design-Automation-Toolkit

Computer Science/Engineering Thesis Project. This is a toolkit to automate and accelerate the design and verification of Systems on Chips (SoCs). It mainly includes a template-based tool for designing SoCs.

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SoC-Design-Automation-Toolkit

Computer Science/Engineering Thesis Project. This is a toolkit to automate and accelerate the design and verification of Systems on Chips (SoCs). It mainly includes a template-based tool for designing SoCs.

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Computer Science/Engineering Thesis Project. This is a toolkit to automate and accelerate the design and verification of Systems on Chips (SoCs). It mainly includes a template-based tool for designing SoCs.


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Language:Verilog 55.2%Language:Python 42.3%Language:Coq 2.5%