XiangShan

OpenXiangShan

Open-source high-performance RISC-V processor

XiangShan's repositories

XiangShan

Open-source high-performance RISC-V processor

Language:ScalaNOASSERTION4486 91 350

XiangShan-doc

Documentation for XiangShan

Language:TeXCC-BY-4.0323 17 29

NEMU

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difftest

Modern co-simulation framework for RISC-V CPUs

Language:C++MulanPSL-2.098 4 26

HuanCun

Open-source high-performance non-blocking cache

Language:ScalaNOASSERTION61 9 15

xs-env

XiangShan Frontend Develop Environment

Language:ShellNOASSERTION41 7 12

nexus-am

Language:C30 2 6

CoupledL2

Open-source non-blocking L2 cache

Language:ScalaNOASSERTION26 40

YunSuan

This repo includes XiangShan's function units

Language:ScalaMulanPSL-2.012 2 1

env-scripts

Scripts for XiangShan

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tl-test

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Utility

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CPU2006LiteWrapper

Language:Makefile6 40

xfuzz

Fuzzing General-Purpose Hardware Designs with Software Fuzzers

Language:ScalaNOASSERTION6 8 2

rocket-chip

Rocket Chip Generator

Language:ScalaNOASSERTION4 20

riscv-isa-sim

Spike, a RISC-V ISA Simulator

Language:CNOASSERTION3 30

riscv-linux

RISC-V Linux Port

Language:CNOASSERTION2 30

LibCheckpoint

Language:C100

opensbi

RISC-V Open Source Supervisor Binary Interface

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riscv-pk

RISC-V Proxy Kernel

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riscv-rootfs

Language:C1 20

tl-test-new

The Unified TileLink Memory Subsystem Tester for XiangShan

Language:C++MulanPSL-2.0100

CPU2017LiteWrapper

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edk2

EDK II

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edk2-platforms

EDK II sample platform branches and tags

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gcc

GPL-2.0001

OpenLLC

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qemu

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

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riscv-hyp-tests

A bare-metal application to test specific features of the risc-v hypervisor extension

Language:CGPL-3.0000

riscv-tests

Language:CNOASSERTION010