Does the loopback test requires amplifier
flyingdorothia opened this issue · comments
Recall #81 : In ZCU111, I currently use DAC226_T0_CH0 (P, N) DAC228_T0_CH1 (N, P) as data generator, I use ADC226_T2_CH1 (P,N) ADC226_T2_CH0 (N,P) as data receiver. The print(QickSoc()) gives me the output ports as:
` 7 signal generator channels:
0: axis_signal_gen_v6 - envelope memory 65536 samples (10.667 us)
fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
DAC tile 0, blk 0 is DAC228_T0_CH0 or RF board output 0
1: axis_signal_gen_v6 - envelope memory 65536 samples (10.667 us)
fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
DAC tile 0, blk 1 is DAC228_T0_CH1 or RF board output 1
2: axis_signal_gen_v6 - envelope memory 65536 samples (10.667 us)
fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
DAC tile 0, blk 2 is DAC228_T0_CH2 or RF board output 2
3: axis_signal_gen_v6 - envelope memory 65536 samples (10.667 us)
fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
DAC tile 1, blk 0 is DAC229_T1_CH0 or RF board output 4
4: axis_signal_gen_v6 - envelope memory 65536 samples (10.667 us)
fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
DAC tile 1, blk 1 is DAC229_T1_CH1 or RF board output 5
5: axis_signal_gen_v6 - envelope memory 65536 samples (10.667 us)
fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
DAC tile 1, blk 2 is DAC229_T1_CH2 or RF board output 6
6: axis_signal_gen_v6 - envelope memory 65536 samples (10.667 us)
fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
DAC tile 1, blk 3 is DAC229_T1_CH3 or RF board output 7
2 readout channels:
0: axis_readout_v2 - controlled by PYNQ
fs=3072.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=3072.000 MHz
maxlen 16384 accumulated, 1024 decimated (2.667 us)
triggered by output 0, pin 14, feedback to tProc input 0
ADC tile 2, blk 0 is ADC226_T2_CH0 or RF board DC input 0
1: axis_readout_v2 - controlled by PYNQ
fs=3072.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=3072.000 MHz
maxlen 16384 accumulated, 1024 decimated (2.667 us)
triggered by output 0, pin 15, feedback to tProc input 1
ADC tile 2, blk 1 is ADC226_T2_CH1 or RF board DC input 1
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But when I loop DAC to ADC with the correct port, it cannot give me a reasonable peak. Can you please like me know, whether I need to put amplifier in between? I have LMH5401 differential and MAX4444 amplifiers. Thank you
If you are using DACs and ADCs with differential connections on the balun board, you are connecting directly to the DC-coupled differential RF-DAC/RF-ADC ports of the FPGA. In general the RF-DAC and RF-ADC ports have different common-mode voltages and you cannot connect the P and N ports directly without a DC-block, baluns, or DC-coupled amplifier with appropriate common-mode voltage.
See the Xilinx docs (links are to the ADC info, but the DAC is in the same documents; the ZCU111's FPGA is a Gen 1/ZU2xDR device):
- https://docs.xilinx.com/r/en-US/ds926-zynq-ultrascale-plus-rfsoc/Integrated-RF-ADC-Block
- https://docs.xilinx.com/r/en-US/pg269-rf-data-converter/RF-ADC-Analog-Input
Is this the same question as #217? It's not a big deal, but please don't open more issues than necessary.