openpower-cores / a2i

openpower-cores/a2i Issues

Fix regression with new GHDL with locally static entity attributes
Closed 2 years ago2
Address space of an SoC using A2I core
Updated 2 years ago2
About some unknow instructions in A2 Core
Updated 2 years ago2
Why msgclr does not set UsesSPR in iuq_fxu_decode.vhdl
Updated 2 years ago
About the memory consistency model in A2
Updated 2 years ago
About the payload bits of msgsnd instruction
Closed 2 years ago2
Error happens when two threads co-execute together
Updated 2 years ago16
Why choosing ex4 to deal with interrupt and exception
Updated 2 years ago2
How to fetch later instructions if a branch instrution is met
Closed 2 years ago1
build and run videos are no longer available
Closed 2 years ago1
The speculative excution of instructions relying on previous loads
Closed 4 years ago2
How to deal with wrong target address prediction of link stack
Updated 3 years ago1
Code not compiling
Closed 3 years ago4
Question regarding the address map of A2i core
Closed 4 years ago8
Question regarding how to drive signal ac_an_req_ld_xfr_len and ac_an_req_ttype (hwsync) of a2l2_axi.vhdl in simulation.
Closed 4 years ago1
A design drawback of thread issue selection?
Updated 4 years ago
Unbalanced instruction fetch latency and instruction fetch width
Closed 4 years ago6
Assistance Required in building A2I core in Vivado Windows
Closed 4 years ago1
Problem in simulation of the a2l2_axi.vhdl file
Updated 4 years ago5
Any hints about the ignore_flush_is0 signal
Updated 4 years ago1
Questions regarding testing A2I with Coremark on FPGA without OS
Closed 4 years ago5
The RAW/WAW dependency check in iuq_fxu_dep.vhdl
Updated 4 years ago1
CoreMark and Simulation
Closed 4 years ago11
Missing testbenches
Closed 4 years ago2
The below water remark in iuq_ib_buff.vhdl
Closed 4 years ago3
L1 cache interface
Closed 4 years ago5
How to quickly find the key information of the combination logics
Closed 4 years ago3
The 'pgsize_eq' of the TLB entries with xbit
Closed 4 years ago4
How to calculate the set number based on the EA (effective address) in the MMU module
Closed 4 years ago11
cache coherency
Closed 4 years ago1
About the "ex3_l_s_q_val" signal in "xuq_lsu_l2cmdq" module
Closed 4 years ago11
about the expand_type
Closed 4 years ago1
Questions about MMQ TLB xbit hole
Closed 4 years ago5
What's the function of field LPID?
Closed 4 years ago1
The order of writing the GPRs
Closed 4 years ago3
The LRU algorithm in I-ERAT
Closed 4 years ago1
Questions about the medium priority when selecting threads to issue
Updated 4 years ago1
How to match the coming effective/virtual address with the given TLB entry when considering the X _bit?
Closed 4 years ago2
How to map the branch prediction algorithm to the RTL code
Updated 4 years ago2
simulation environment
Closed 4 years ago17
How could i simulaion it in vivado or any other tools?
Closed 4 years ago8
Resources required?
Closed 4 years ago1