Encountering Error in Make While Simulating Core CVW with Questasim
waseem-10xe opened this issue · comments
I am simulating the core CVW .After following the steps outlined in the Git repository for setting up the CVW core simulation environment, I executed the source ./setup.sh command to ensure all configurations were appropriately adjusted, including path changes. However, upon running the make command to initiate the build process, I encountered the above error.
Can you check that riscof is installed and in the PATH?
which riscof
/home/rose/.local/bin/riscof
If it's in the path can you run make in cvw/sim and report the error message?
@ross144 here is a log:
make -C ../tests/riscof/
make[1]: Entering directory '/home/qabid/cvw/tests/riscof'
mkdir -p ./riscof_work
mkdir -p ./work
mkdir -p ./work/riscv-arch-test
mkdir -p ./work/wally-riscv-arch-test
sed 's,{0},/home/qabid/cvw/tests/riscof,g;s,{1},32gc,g' config.ini > config32.ini
sed 's,{0},/home/qabid/cvw/tests/riscof,g;s,{1},64gc,g' config.ini > config64.ini
sed 's,{0},/home/qabid/cvw/tests/riscof,g;s,{1},32e,g' config.ini > config32e.ini
riscof run --work-dir=./riscof_work --config=config32.ini --suite=../../addins/riscv-arch-test/riscv-test-suite/ --env=../../addins/riscv-arch-test/riscv-test-suite/env --no-browser
�[32m INFO�[0m | �[32m****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******�[0m
�[32m INFO�[0m | �[32musing riscv_isac version : 0.18.0�[0m
�[32m INFO�[0m | �[32musing riscv_config version : 3.14.3�[0m
�[32m INFO�[0m | �[32mReading configuration from: /home/qabid/cvw/tests/riscof/config32.ini�[0m
�[32m INFO�[0m | �[32mPreparing Models�[0m
�[32m INFO�[0m | �[32mInput-ISA file�[0m
�[32m INFO�[0m | �[32mLoading input file: /home/qabid/cvw/tests/riscof/spike/spike_rv32gc_isa.yaml�[0m
�[32m INFO�[0m | �[32mLoad Schema /usr/local/lib/python3.10/dist-packages/riscv_config/schemas/schema_isa.yaml�[0m
�[32m INFO�[0m | �[32mProcessing Hart: hart0�[0m
�[32m INFO�[0m | �[32mInitiating Validation�[0m
�[32m INFO�[0m | �[32mNo errors for Hart: 0 :)�[0m
�[32m INFO�[0m | �[32m Updating fields node for each CSR�[0m
�[32m INFO�[0m | �[32mDumping out Normalized Checked YAML: /home/qabid/cvw/tests/riscof/riscof_work/spike_rv32gc_isa_checked.yaml�[0m
�[32m INFO�[0m | �[32mInput-Platform file�[0m
�[32m INFO�[0m | �[32mLoading input file: /home/qabid/cvw/tests/riscof/spike/spike_platform.yaml�[0m
�[32m INFO�[0m | �[32mLoad Schema /usr/local/lib/python3.10/dist-packages/riscv_config/schemas/schema_platform.yaml�[0m
�[32m INFO�[0m | �[32mInitiating Validation�[0m
�[32m INFO�[0m | �[32mNo Syntax errors in Input Platform Yaml. :)�[0m
�[32m INFO�[0m | �[32mDumping out Normalized Checked YAML: /home/qabid/cvw/tests/riscof/riscof_work/spike_platform_checked.yaml�[0m
�[32m INFO�[0m | �[32mGenerating database for suite: /home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite�[0m
�[32m INFO�[0m | �[32mDatabase File Generated: /home/qabid/cvw/tests/riscof/riscof_work/database.yaml�[0m
�[32m INFO�[0m | �[32mEnv path set to/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/env�[0m
�[32m INFO�[0m | �[32mRunning Build for DUT�[0m
�[32m INFO�[0m | �[32mRunning Build for Reference�[0m
�[32m INFO�[0m | �[32mSelecting Tests.�[0m
�[32m INFO�[0m | �[32mRunning Tests on DUT.�[0m
�[32m INFO�[0m | �[32mRunning Tests on Reference Model.�[0m
�[32m INFO�[0m | �[32mInitiating signature checking.�[0m
�[32m INFO�[0m | �[32mFollowing 451 tests have been run :
�[0m
�[32m INFO�[0m | �[32mTEST NAME : COMMIT ID : STATUS�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoadd.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoand.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amomax.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amomaxu.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amomin.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amominu.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoor.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoswap.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/andn-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bclr-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bclri-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bext-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bexti-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/binv-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/binvi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bset-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bseti-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/clmul-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/clmulh-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/clmulr-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/clz-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/cpop-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/ctz-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/max-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/maxu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/min-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/minu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/orcb_32-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/orn-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/rev8_32-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/rol-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/ror-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/rori-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sext.b-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sext.h-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sh1add-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sh2add-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sh3add-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/xnor-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/zext.h_32-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cand-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/candi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbnez-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cebreak-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cj-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjal-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjalr-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjr-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cli-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clui-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clw-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clwsp-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cmv-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cnop-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cor-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cslli-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrai-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrli-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csub-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csw-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cswsp-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cxor-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b10-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b11-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b12-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b13-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fadd.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fclass.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.w_b25-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.w_b26-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.wu_b25-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.d.wu_b26-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b22-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b23-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b24-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b27-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b28-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b29-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b22-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b23-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b24-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b27-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b28-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b29-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b22-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b23-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b24-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b27-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b28-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b29-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b20-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b21-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fdiv.d_b9-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/feq.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/feq.d_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fld-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fle.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fle.d_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/flt.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/flt.d_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b14-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b15-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b16-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b17-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b18-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmadd.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmax.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmax.d_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmin.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmin.d_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b14-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b15-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b16-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b17-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b18-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmsub.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fmul.d_b9-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b14-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b15-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b16-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b17-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b18-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmadd.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b14-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b15-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b16-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b17-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b18-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fnmsub.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsd-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsgnj.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsgnjn.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsgnjx.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b20-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fsqrt.d_b9-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b10-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b11-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b12-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b13-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/D/src/fssub.d_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b10-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b11-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b12-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b13-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fadd_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fclass_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.s.w_b25-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.s.w_b26-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.s.wu_b25-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.s.wu_b26-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b22-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b23-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b24-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b27-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b28-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.w.s_b29-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b22-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b23-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b24-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b27-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b28-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fcvt.wu.s_b29-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b20-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b21-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fdiv_b9-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/feq_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/feq_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fle_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fle_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flt_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flt_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b14-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b15-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b16-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b17-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b18-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmadd_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmax_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmax_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmin_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmin_b19-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b14-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b15-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b16-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b17-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b18-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmsub_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmul_b9-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.w.x_b25-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.w.x_b26-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b22-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b23-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b24-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b27-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b28-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fmv.x.w_b29-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b14-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b15-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b16-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b17-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b18-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmadd_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b14-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b15-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b16-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b17-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b18-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b6-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fnmsub_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsgnj_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsgnjn_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsgnjx_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b20-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsqrt_b9-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b10-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b11-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b12-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b13-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b2-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b3-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b5-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b7-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsub_b8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsw-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/misalign1-jalr-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/aes32dsi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/aes32dsmi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/aes32esi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/aes32esmi-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/brev8_32-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/pack-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/packh-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha256sig0-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha256sig1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha256sum0-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha256sum1-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha512sig0h-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha512sig0l-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha512sig1h-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha512sig1l-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha512sum0r-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/sha512sum1r-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/unzip-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/xperm4-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/xperm8-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/zip-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/div-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/divu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mul-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulh-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/rem-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/remu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/Zicond/src/czero.eqz-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/Zicond/src/czero.nez-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/src/Fencei.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/ebreak.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/ecall.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S : - : Passed�[0m
�[32m INFO�[0m | �[32mTest report generated at /home/qabid/cvw/tests/riscof/riscof_work/report.html.�[0m
rsync -a ./riscof_work/rv32i_m/ ./work/riscv-arch-test/rv32i_m/ || echo "error suppressed"
riscof run --work-dir=./riscof_work --config=config32.ini --suite=../wally-riscv-arch-test/riscv-test-suite/ --env=../wally-riscv-arch-test/riscv-test-suite/env --no-browser --no-dut-run
�[32m INFO�[0m | �[32m****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******�[0m
�[32m INFO�[0m | �[32musing riscv_isac version : 0.18.0�[0m
�[32m INFO�[0m | �[32musing riscv_config version : 3.14.3�[0m
�[32m INFO�[0m | �[32mReading configuration from: /home/qabid/cvw/tests/riscof/config32.ini�[0m
�[32m INFO�[0m | �[32mPreparing Models�[0m
�[32m INFO�[0m | �[32mInput-ISA file�[0m
�[32m INFO�[0m | �[32mLoading input file: /home/qabid/cvw/tests/riscof/spike/spike_rv32gc_isa.yaml�[0m
�[32m INFO�[0m | �[32mLoad Schema /usr/local/lib/python3.10/dist-packages/riscv_config/schemas/schema_isa.yaml�[0m
�[32m INFO�[0m | �[32mProcessing Hart: hart0�[0m
�[32m INFO�[0m | �[32mInitiating Validation�[0m
�[32m INFO�[0m | �[32mNo errors for Hart: 0 :)�[0m
�[32m INFO�[0m | �[32m Updating fields node for each CSR�[0m
�[32m INFO�[0m | �[32mDumping out Normalized Checked YAML: /home/qabid/cvw/tests/riscof/riscof_work/spike_rv32gc_isa_checked.yaml�[0m
�[32m INFO�[0m | �[32mInput-Platform file�[0m
�[32m INFO�[0m | �[32mLoading input file: /home/qabid/cvw/tests/riscof/spike/spike_platform.yaml�[0m
�[32m INFO�[0m | �[32mLoad Schema /usr/local/lib/python3.10/dist-packages/riscv_config/schemas/schema_platform.yaml�[0m
�[32m INFO�[0m | �[32mInitiating Validation�[0m
�[32m INFO�[0m | �[32mNo Syntax errors in Input Platform Yaml. :)�[0m
�[32m INFO�[0m | �[32mDumping out Normalized Checked YAML: /home/qabid/cvw/tests/riscof/riscof_work/spike_platform_checked.yaml�[0m
�[32m INFO�[0m | �[32mGenerating database for suite: /home/qabid/cvw/tests/wally-riscv-arch-test/riscv-test-suite�[0m
�[32m INFO�[0m | �[32mDatabase File Generated: /home/qabid/cvw/tests/riscof/riscof_work/database.yaml�[0m
�[32m INFO�[0m | �[32mEnv path set to/home/qabid/cvw/tests/wally-riscv-arch-test/riscv-test-suite/env�[0m
�[32m INFO�[0m | �[32mRunning Build for Reference�[0m
�[32m INFO�[0m | �[32mSelecting Tests.�[0m
�[32m INFO�[0m | �[32mRunning Tests on Reference Model.�[0m
�[32m INFO�[0m | �[32mTests run on Reference done.�[0m
rsync -a ./riscof_work/rv32i_m/ ./work/wally-riscv-arch-test/rv32i_m/ || echo "error suppressed"
riscof run --work-dir=./riscof_work --config=config32e.ini --suite=../../addins/riscv-arch-test/riscv-test-suite/ --env=../../addins/riscv-arch-test/riscv-test-suite/env --no-browser
�[32m INFO�[0m | �[32m****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******�[0m
�[32m INFO�[0m | �[32musing riscv_isac version : 0.18.0�[0m
�[32m INFO�[0m | �[32musing riscv_config version : 3.14.3�[0m
�[32m INFO�[0m | �[32mReading configuration from: /home/qabid/cvw/tests/riscof/config32e.ini�[0m
�[32m INFO�[0m | �[32mPreparing Models�[0m
�[32m INFO�[0m | �[32mInput-ISA file�[0m
�[32m INFO�[0m | �[32mLoading input file: /home/qabid/cvw/tests/riscof/spike/spike_rv32e_isa.yaml�[0m
�[32m INFO�[0m | �[32mLoad Schema /usr/local/lib/python3.10/dist-packages/riscv_config/schemas/schema_isa.yaml�[0m
�[32m INFO�[0m | �[32mProcessing Hart: hart0�[0m
�[32m INFO�[0m | �[32mInitiating Validation�[0m
�[32m INFO�[0m | �[32mNo errors for Hart: 0 :)�[0m
�[32m INFO�[0m | �[32m Updating fields node for each CSR�[0m
�[32m INFO�[0m | �[32mDumping out Normalized Checked YAML: /home/qabid/cvw/tests/riscof/riscof_work/spike_rv32e_isa_checked.yaml�[0m
�[32m INFO�[0m | �[32mInput-Platform file�[0m
�[32m INFO�[0m | �[32mLoading input file: /home/qabid/cvw/tests/riscof/spike/spike_platform.yaml�[0m
�[32m INFO�[0m | �[32mLoad Schema /usr/local/lib/python3.10/dist-packages/riscv_config/schemas/schema_platform.yaml�[0m
�[32m INFO�[0m | �[32mInitiating Validation�[0m
�[32m INFO�[0m | �[32mNo Syntax errors in Input Platform Yaml. :)�[0m
�[32m INFO�[0m | �[32mDumping out Normalized Checked YAML: /home/qabid/cvw/tests/riscof/riscof_work/spike_platform_checked.yaml�[0m
�[32m INFO�[0m | �[32mGenerating database for suite: /home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite�[0m
�[32m INFO�[0m | �[32mDatabase File Generated: /home/qabid/cvw/tests/riscof/riscof_work/database.yaml�[0m
�[32m INFO�[0m | �[32mEnv path set to/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/env�[0m
�[32m INFO�[0m | �[32mRunning Build for DUT�[0m
�[32m INFO�[0m | �[32mRunning Build for Reference�[0m
�[32m INFO�[0m | �[32mSelecting Tests.�[0m
�[32m INFO�[0m | �[32mRunning Tests on DUT.�[0m
�[1;31m ERROR�[0m | �[1;31mmake[2]: Entering directory '/home/qabid/cvw/tests/riscof/riscof_work'
make[2]: Leaving directory '/home/qabid/cvw/tests/riscof/riscof_work'�[0m
�[1;31m ERROR�[0m | �[1;31m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32e_m/E/src/jalr-01.S: Assembler messages:
/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32e_m/E/src/jalr-01.S:73: Error: illegal operands `la x0,5b'
terminate called after throwing an instance of 'std::runtime_error'
what(): could not open my.elf; searched paths:
. (current directory)
/riscv64-unknown-elf/bin/ (based on configured --prefix and --with-target)
make[2]: *** [/home/qabid/cvw/tests/riscof/riscof_work/Makefile.DUT-spike:165: TARGET40] Error 255
make[2]: *** Waiting for unfinished jobs....�[0m
�[32m INFO�[0m | �[32mRunning Tests on Reference Model.�[0m
�[1;31m ERROR�[0m | �[1;31mmake[2]: Entering directory '/home/qabid/cvw/tests/riscof/riscof_work'
make[2]: Leaving directory '/home/qabid/cvw/tests/riscof/riscof_work'�[0m
�[1;31m ERROR�[0m | �[1;31m/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32e_m/E/src/jalr-01.S: Assembler messages:
/home/qabid/cvw/addins/riscv-arch-test/riscv-test-suite/rv32e_m/E/src/jalr-01.S:73: Error: illegal operands `la x0,5b'
riscv64-unknown-elf-objdump: 'ref.elf': No such file
make[2]: *** [/home/qabid/cvw/tests/riscof/riscof_work/Makefile.Reference-sail_c_simulator:165: TARGET40] Error 1
make[2]: *** Waiting for unfinished jobs....�[0m
�[32m INFO�[0m | �[32mInitiating signature checking.�[0m
�[1;31m ERROR�[0m | �[1;31mSignature file : /home/qabid/cvw/tests/riscof/riscof_work/rv32e_m/E/src/jalr-01.S/dut/DUT-spike.signature does not exist�[0m
make[1]: *** [Makefile:24: arch32e] Error 1
make[1]: Leaving directory '/home/qabid/cvw/tests/riscof'
make: *** [Makefile:52: riscoftests] Error 2
riscv-arch-test is out of date for you. You'll need to pull a corrected version.
cd $WALLY/addins/riscv-arch-test
git pull
Thanks, @ross144, @quswarabid, and @davidharrishmc for your help in resolving the issue.