Bug : MTVAL is not read-only zero
AyoubJalali opened this issue · comments
Hello, in the CV32A65X configuration the mtval is read-only zero (doesn't not raise an exception if we write into it), is means we only have the zero value in it, but Spike isn't aligned and store the instruction causes the exception into it, the bug appears in both solo and tandem mode.
TANDEM :
SOLO :
The CVA3265X User Manual states that the mtval register is an MXLEN-bit read-only 0 register, so I think the RTL is doing the right thing.
This is yet-another Spike configuration issue.
It should be configurable using the new PR on cvv #2465
It should be configurable using the new PR on cvv #2465
The construction of the mask/value can be automated once the Yaml-based Spike config is in place: the riscv-config description states clearly which fields of each CSR are "RO zero". For mtval the field is the entire 32 bits...