openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Home Page:https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html

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[cv_dv_utils] rd_res_ex_fail signal is not driven in memory response model

khandelwaltanuj opened this issue · comments

Hello,

The signal rd_res_ex_fail is never driven. In the case of exclusive read, the memory response model should respond with either pass or fail. It does correctly in the case of write but it does nothing in the case of a read.

Thanks and regards
Tanuj

Hi @khandelwaltanuj, thanks for your interest in OpenHW. I assume you are referring to lib/cv_dv_utils/uvm/memory_rsp_model/memory_response_if.sv. Please confirm.

Hi @ludovicpion, can you comment?

Thanks for the confirmation @ludovicpion. Can you answer @khandelwaltanuj's question as to why the signal rd_res_ex_fail is never driven?

Hi @MikeOpenHWGroup
I found this issue while working on the verification of different configuration of HPDcache.
We have fixed this issue locally.
Once we are satisfied, we will do a merge request.

Thanks and Regards
Tanuj Khandelwal

Hi @khandelwaltanuj, please close this issue if you are satisfied it is fixed now that #2390 is merged in. Thanks!

Thanks for the merge.

Regards
Tanuj