make error

[vidushiy25]

Hi, I was using the CORE-V-VERIF Quick Start Guide to compile a hello world test program as stated in it but when I do make it gives me the following error:

%Warning-MULTIDRIVEN: /home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:291:9: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'data_req_dec'
: ... In instance tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:291:9:
291 | data_req_dec = '0;
| ^~~~~~~~~~~~
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:196:8: ... Location of other write
196 | data_req_dec = data_req_i;
| ^~~~~~~~~~~~
... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=5.008
... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
%Warning-MULTIDRIVEN: /home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:292:9: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'data_addr_dec'
: ... In instance tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:292:9:
292 | data_addr_dec = '0;
| ^~~~~~~~~~~~~
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:205:11: ... Location of other write
205 | data_addr_dec = data_addr_i[RAM_ADDR_WIDTH-1:0];
| ^~~~~~~~~~~~~
%Warning-MULTIDRIVEN: /home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:293:9: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'data_wdata_dec'
: ... In instance tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:293:9:
293 | data_wdata_dec = '0;
| ^~~~~~~~~~~~~~
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:208:8: ... Location of other write
208 | data_wdata_dec = data_wdata_i;
| ^~~~~~~~~~~~~~
%Warning-MULTIDRIVEN: /home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:294:9: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'data_we_dec'
: ... In instance tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:294:9:
294 | data_we_dec = '0;
| ^~~~~~~~~~~
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:209:8: ... Location of other write
209 | data_we_dec = data_we_i;
| ^~~~~~~~~~~%Warning-MULTIDRIVEN: /home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:295:9: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'data_be_dec'
: ... In instance tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:295:9:
295 | data_be_dec = '0;
| ^~~~~~~~~~~
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:210:8: ... Location of other write
210 | data_be_dec = data_be_i;
| ^~~~~~~~~~~
%Warning-MULTIDRIVEN: /home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:312:9: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'transaction'
: ... In instance tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:312:9:
312 | transaction = T_PER;
| ^~~~~~~~~~~
/home/parallels/core-v-verif/cv32e40p/tb/core/mm_ram.sv:211:8: ... Location of other write
211 | transaction = T_RAM;
| ^~~~~~~~~~~
%Warning-COMBDLY: /home/parallels/core-v-verif/core-v-cores/cv32e40p/rtl/../bhv/cv32e40p_sim_clock_gate.sv:25:31: Non-blocking assignment '<=' in combinational logic process
: ... This will be executed as a blocking assignment '='!
25 | if (clk_i == 1'b0) clk_en <= en_i | scan_cg_en_i;
| ^~
*** See https://verilator.org/warn/COMBDLY before disabling this,
else you may end up with different sim results.
%Error: Exiting due to 7 warning(s)
make[1]: *** [Makefile:491: testbench_verilator] Error 1
make[1]: Leaving directory '/home/parallels/core-v-verif/cv32e40p/sim/core'
make: *** [Makefile:485: sanity-veri-run] Error 2