Unable to run CV32E40S and CV32E40X cores
nerdylye opened this issue · comments
Hi all, I am getting this error while running hello-world, I did not modify anything and just ran the make command. Thanks in advance.
The command I used to run is make veri-test TEST=hello-world with Verilator version 5.012
The toolchain I used is from RISC-V Compiler Toolchain - lowRISC provides a pre-built GCC based toolchain
The syntax line in question is a SystemVerilog "in-line" casting assignment that is perfectly legal syntax. All known commercial SystemVerilog simulators correctly compile and execute this construct as expected.
This is either a bug or a not-yet-implemented feature in Verilator, not a problem in either the CV32E40S/E40X cores or in CORE-V-VERIF.