omutlu

rowhammer-test

Test DRAM for bit flips caused by the rowhammer problem

ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

RowPress

Source code & scripts for experimental characterization and real-system demonstration of RowPress, a widespread read disturbance phenomenon in DRAM that is different from RowHammer. Described in our ISCA'23 paper by Luo et al. at https://people.inf.ethz.ch/omutlu/pub/RowPress_isca23.pdf

Victima

Victima is a new software-transparent technique that greatly extends the address translation reach of modern processors by leveraging the underutilized resources of the cache hierarchy, as desribed in the MICRO 2023 paper by Kanellopoulos et al. (https://arxiv.org/pdf/2310.04158/)

Virtuoso

Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.

SPARTA

A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https://arxiv.org/pdf/2303.03509.pdf)

SimplePIM

SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 2023 paper by Chen et al. (https://arxiv.org/pdf/2310.01893.pdf).

moesi-prime

ABACuS

New RowHammer mitigation mechanism that is area-, performance-, and energy-efficient especially at very low (e.g., 125) RowHammer thresholds, as described in the USENIX Security'24 paper https://arxiv.org/pdf/2310.09977.pdf

CLRDRAM

Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf

FCDRAM

Source code & scripts for experimental characterization and demonstration of performing NOT and up to 16-input AND, NAND, OR, and NOR operations in real DDR4 DRAM chips. Described in our HPCA'24 paper by Yuksel et al. at https://arxiv.org/abs/2402.18736

CoMeT

CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper https://arxiv.org/pdf/2402.18769.pdf

GateSeeder

GateSeeder is the first near-memory CPU-FPGA co-design for alleviating both the compute-bound and memory-bound bottlenecks in short and long-read mapping. GateSeeder outperforms Minimap2 by up to 40.3×, 4.8×, and 2.3× when mapping real ONT, HiFi, and Illumina reads, respectively.

MIMDRAM

Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing''. Paper is at: https://arxiv.org/pdf/2402.19080.pdf

DRAM-Voltage-Study

Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs

MIG-7-PHY-DDR3-Controller

A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.

RawAlign

RawAlign is a real-time raw nanopore read mapper based on the Seed-Filter-Align paradigm as described by Lindegger et al. (https://arxiv.org/abs/2310.05037)

UHMEM

A cycle-accurate simulator that models a hybrid memory subsystem consisting of multiple memory technologies. Described in the CLUSTER 2017 paper by Li et al. (https://people.inf.ethz.ch/omutlu/pub/utility-based-hybrid-memory-management_cluster17.pdf)

LEAP

MetaTrinity

MetaTrinity is a novel metagenomic analysis tool employing efficient containment search techniques and heuristics for read mapping to achieve significant speedup while maintaining high accuracy. This positions MetaTrinity as an efficient solution, optimally balancing speed and precision in metagenomic analysis.

SMLA

This simulator models Simultaneous Multi Layer Access (SMLA) and 3D-stacked DRAM memory, based on the TACO 2016 paper https://users.ece.cmu.edu/~omutlu/pub/smla_high-bandwidth-3d-stacked-memory_taco16.pdf

ThyNVM

ThyNVM: Transparent hybrid NonVolatile Memory. A gem5-based persistent memory simulator that implements a DRAM+NVM hybrid memory architecture. Introduced in the MICRO 2015 paper: https://users.ece.cmu.edu/~omutlu/pub/ThyNVM-transparent-crash-consistency-for-persistent-memory_micro15.pdf

Utopia

Utopia is a new hybrid address mapping scheme that accelerates address translation while supporting all conventional VM features as described by Kanellopoulos et al. (https://arxiv.org/abs/2211.12205)

Register-Interval

LTRF's register-interval creation algorithm divides the control flow graph (CFG) of a GPU application into some register-intervals which have two main characteristics: 1) register-intervals have only one entry-point in CFG, and 2) they have a limited number of registers. This algorithm is part of ASPLOS2018 paper by Sadrosadati et al. at https://people.inf.ethz.ch/omutlu/pub/LTRF-latency-tolerant-GPU-register-file_asplos18.pdf

Rubicon

RUBICON is a novel framework to automatically develop deep-learning-based genomic basecallers for any given architecture, as described in our Genome Biology'24 paper https://genomebiology.biomedc

sasiml

An extensible and fully programable cycle-accurate Spatial Architecture simulator for Machine Learning Workloads. Described in detail in the IEEE TC 2023 paper by Orosa et al. at https://arxiv.org/abs/2202.02310

alignment-in-memory

AIM (Alignment-in-Memory), A Framework for High-throughput Sequence Alignment using Real Processing-in-Memory Systems, Bioinformatics, btad155, https://doi.org/10.1093/bioinformatics/btad155

DRAM-Latency-Variation-Study

Latency characterization data collected from 30 real DRAM SO-DIMMs. You can find the background and analysis on the data in our SIGMETRICS'16 paper "Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization".

MeDiC

This is a patch on GPGPU-sim for MeDiC. MeDiC is a mechanism that reduces the negative performance impact of memory divergence and cache queuing in GPUs. It is introduced in the PACT 2015 paper by Ausavarungnirun et al. at http://users.ece.cmu.edu/~omutlu/pub/MeDiC-for-GPGPUs_pact15.pdf

SequenceLab

SequenceLab is a benchmark suite for evaluating computational methods for comparing genomic sequences, such as pre-alignment filters and pairwise sequence alignment algorithms. SequenceLab is described by Rumpf et al. at https://arxiv.org/abs/2310.16908