Omkar Bhilare's repositories
riscv-core
A customized RISCV core made using verilog
vga-interface-with-TANG-PRIMER-FPGA
Interfacing Tang primer with VGA display.
Aqua_Farm_Monitor
ESP32 Based IOT system to monitor Aqua Farming
Carry-Lookahead-Adder-Cocotb
Verification test of Carry Lookahead Adder using cocotb
Seven-Segment-with-Tang-Primer-FPGA
Seven Segment Interface with Tang Primer
SRA-BOARD-2020
SRA development board is a esp32 based board with components on board like motor driver, switches and leds.
100DaysOfRTL
100 Days of RTL
BeagleWire
This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/
caravel_user_project
https://caravel-user-project.readthedocs.io
icebreaker-ecp5-examples
Examples for icebreaker ++ board
Interconnect-from-scratch-in-chisel
Communication Between two FSMs in chisel
8-Bit-ALU-implementation-on-CYCLONE-2
Verilog code for 8 Bit ALU and implemented on Intel's Cyclone II
basil
A data acquisition framework in Python and Verilog.
gsoc-proposals-archive
This repository contains Accepted proposals for various Google Summer of Code organizations throughout various years!
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
litedram
Small footprint and configurable DRAM core
litex-boards
LiteX boards files
ombhilare999.github.io
https://ombhilare999.github.io/
PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
QuantaRV
Serial 32bit RISCV Core
sra-board-component
ESP-IDF component for SRA Board
sra-board-hardware-design
ESP32-based Development Board for Robotics and Embedded Applications
sra-vjti.github.io
Repository for SRA Website
Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
Wall-E_v2.2-beta
Development Repository for Wall-E v2.2