oaltinay

ascon

Implements ASCON Cryptography algorithm for a RISC-V processor which is extended with custom instructions for ASCON.

CarND-Advanced-Lane-Lines

CarND-Behavioral-Cloning-P3

CarND-LaneLines-P1

CppND-Memory-Management-Chatbot

CppND-Program-a-Concurrent-Traffic-Simulation

CppND-Route-Planning-Project

CppND-System-Monitor

Traffic-Sign-Classifier-Project

riscv-binutils-gdb

Fork to add RISC-V extended instructions for ASCON cryptography algorithm.

riscv-gcc

Fork to add RISC-V specific GCC built-in functions and machine descriptions for extended instructions for ASCON cryptography algorithm.

riscv-isa-sim

Fork to add extended RISC-V instructions to Spike, a RISC-V ISA Simulator, for ASCON cryptography algorithm. Counts clock cycles of the new instructions and simulates for a RISC-V processor.

CarND-Traffic-Sign-Classifier-Project

Udacity Self Driving Car NanoDegree Project 3

dcl115-2021-apr-26

DCL-115: Multi-Threaded Programming in C++17

design_patterns

freedom-tools

Tools for SiFive's Freedom Platform

pulp-riscv-gcc

riscv-tools

RISC-V Tools (ISA Simulator and Tests)