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nturley / tuesday

Experimenting with turning NVC VHDL simulator into a VHDL parsing library

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tuesday

Experimenting with turning NVC VHDL simulator into a VHDL parsing library

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Experimenting with turning NVC VHDL simulator into a VHDL parsing library

License:GNU General Public License v3.0

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Language:VHDL 62.5%Language:C 35.5%Language:CMake 2.0%