npranavb

Nexys-A7-100T-GPIO

FemtoRV32-Piplined-Processor

The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

A-Pipelined-RISCV-Core

A 5 Stage Pipelined RISC V Core deigned using Verilog HDL.

RISC-V-Vector-Processor

256-bit vector processor based on the RISC-V vector (V) extension

hacktoberfest2022

Hacktoberfest2022 - Contribute given programs in any language you want, every valid PR will be accepted!!!

RISC-V

Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

Algorithm

Basic Data Structure Algorithm in C++