noname's repositories
AutoSVA
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
awesome-hardware-tools
List of awesome open source hardware tools
awesome-hdl
Hardware Description Languages
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
batchRun
batchRun is an ansible-similar IT automation system, which is more suitable for IC industry.
bender
A dependency management tool for hardware projects.
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
coverage
Implementation of post-process coverage, and batch waveform search
drawio
Source to app.diagrams.net
fusesoc-cores
FuseSoC standard core library
HDLGen
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
ic_flow_platform
IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow contral.
JSONinSV
JSON lib in Systemverilog
noVNC
VNC client web application
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
pulp-runtime
Simple runtime for Pulp platforms
pulp_cluster
The multi-core cluster of a PULP system.
pysv
Running Python code in SystemVerilog
pyuvm
The UVM written in Python
qemu
Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
uvm_testbench_gen
Novel GUI Based UVM Testbench Template Builder
vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
wb2axip
Bus bridges and other odds and ends