nmoroze

swap

Swap is a new (award winning) take on the classic tile-based puzzle game, where you change which character you're controlling to reach your goal.

lemoncore

Simple RISC-V processor for FPGAs :lemon: :robot:

tclint

A CLI utility for linting and analyzing Tcl code.

kronos

My MEng thesis code - verifying a security property for an SoC with Rosette

printer

CAD files for custom 3D printer design. Inspired by Prusa i3.

nmoroze.github.io

My personal site.

dotfiles

My dotfiles

notary

Notary: A Device for Secure Transaction Approval 📟

opentitan-kronos

Fork of OpenTitan with modifications for Kronos

AVH-GetStarted

blog

Personal blog for writing about my projects

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

guitarpi

rock n roll

linux

Linux kernel source tree

netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

oh

Verilog library for ASIC and FPGA designers

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

opentitan

OpenTitan: Open source silicon root of trust

opentitan-sv2v

Build flow to convert the OpenTitan to Verilog.

personal-site-archive

Archived personal project portfolio

Prusai3-Marlin

Marlin configuration for custom Prusa i3

redisred

A small Redis-based URL Redirector

riscv-formal

RISC-V Formal Verification Framework

rtlv

Tools for reasoning about circuits in Rosette/Racket 🔌

sby-experiments

siliconcompiler

A modular build system for hardware

Slic3r-Config

Config files for Slic3r.

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

wavy

yosys

Yosys Open SYnthesis Suite