Nikolaos Kavvadias's repositories
yosys-examples
Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
fixed_extensions
VHDL fixed-point arithmetic extensions package
complexpack
complexpack is a complex arithmetic package written in VHDL.
color_maker-s3esk
A simple VGA output tester for the Xilinx Spartan-3E starter kit board.
bstest-s3esk
A buttons, switches and LEDs tester for the Xilinx Spartan-3E starter kit board.
elemapprox
Approximating and plotting elementary functions as ASCII or bitmap for ANSI C, Verilog and VHDL
vhdl-examples
VHDL examples for simulation and synthesis
ledramp-s3esk
LED ramp effect on the Xilinx Spartan-3E starter kit board.
liveanalysis
Liveness analysis pass for Machine-SUIF