nitishsameer's repositories
AccelGame
AcceleratorPlus 2 - A simple one-class game written in Java.
awesome-cpp
A curated list of awesome C++ (or C) frameworks, libraries, resources, and shiny things. Inspired by awesome-... stuff.
CODWISE-Problems
Problem name and my solutions
CPP-and-Algorithms
A collection of various C++ and algorithms concepts
DataStructures-Algorithms
The best library for implementation of all Data Structures and Algorithms - Trees + Graph Algorithms too!
Image_Processing_Laboratory_IITKGP
Digital Image Processing Laboratory Spring 2016
interview
📚 C/C++ 技术面试基础知识总结，包括语言、程序库、数据结构、算法、系统、网络、链接装载库等知识及面试经验、招聘、内推等信息。This repository is a summary of the basic knowledge of recruiting job seekers and beginners in the direction of C/C++ technology, including language, program library, data structure, algorithm, system, network, link loading library, interview experience, recruitment, recommendation, etc.
LeetCode
Solutions to LeetCode Problems
modern-cpp-features
A cheatsheet of modern C++ language and library features.
resume.github.com
Resumes generated using the GitHub informations
Verilog-Programming
This repository will provide you programming examples of various Digital Circuits using Verilog.
Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
vsdstdcelldesign
This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.