Ninad Jangle 's repositories
Block_Based_Circuit_Design
GSoC 2021, FOSSi Foundation
riscv-cpu-core
A pipelined RISC-V CPU Core Implemented in Makerchip using TL-Verilog
verilog-examples
test code for anyone learning the language verilog
flexus
Contains the code for the Flexus cycle-accurate simulator, used in QFlex.
fos-proposals
:gift_heart: :penguin: Archive of GSoC proposals
gecko-dev-riscv
Read-only Git mirror of the Mercurial gecko repositories at https://hg.mozilla.org. How to contribute: http://bit.ly/contribute-code
Intro_to_CV
SRA's seminar on Introduction to Computer Vision Fundamentals
libqflex
Contains the API used for interfacing between QEMU and Flexus.
ninja3011.github.io
Portfolio website codebase for ninadjangle.com
Obstacle-Avoidance-using-ROS-and-Gazebo
A VJTI SRA problem statement
ombhilare999.github.io
https://omkarbhilare.tech/
qemu
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
qflex
Quick & Flexible Rack-Scale Computer Architecture Simulator
React-Snippets
JPMC
risc-v-core
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
riscv-core
A customized RISCV core made using verilog
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
riscv-simple-sv
A simple RISC V core for teaching
sra-vjti.github.io
Repository for SRA Website
Wall-E_v2.2-beta
Development Repository for Wall-E v2.2