This is a reference design for SPI slave to simple memory mapped bus master, which could be used as IO hub or sensor hub in any elec-system.
- Quartus Prime 18.0 Lite
- ModelSim (Intel FPGA Starter Edition) 10.5b
- STEP FPGA MAX10 Board
SPI Slave to Memory Mapped Bus Reference Design
This is a reference design for SPI slave to simple memory mapped bus master, which could be used as IO hub or sensor hub in any elec-system.
SPI Slave to Memory Mapped Bus Reference Design
Apache License 2.0