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nightseas / rockchili-iohub

Verilog reference design for common IO hub or sensor hub which could be used in any elec-system.

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Rock Chili PLD Project

This is a reference verilog design for common IO hub or sensor hub which could be used in any elec-system (etc. communication equipment, FPGA accelerator card).

EDA Tools

  • Quartus Prime 18.0 Lite
  • ModelSim (Intel FPGA Starter Edition) 10.5b

Verified Platform

  • FPGA-B Reference Board (MAXV CPLD)

About

Verilog reference design for common IO hub or sensor hub which could be used in any elec-system.

License:Apache License 2.0

Languages

Language:Verilog 100.0%