nguyenquanicd

UvmEnvUartApb

This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetigating the UVM env.

AllArbiterRTLCode

RTL code of some arbitration algorithm

FirstX2P

This is the AXI-to-APB bridge which only supports convert AXI-32bit to APB-32 bit

SystemCScpuCA

This is the example of Cycle Accurate (CA) model. It is the Simple CPU (SCPU) is described in SystemC language.

VG_RTL

All RTL codes of VG project

apbUartUvmSystemC

A SystemC UVM environment for UART-APB

AsyncFIFO

An asyncchronous FIFO

AXI4VIP

AXI4 VIP supports both AXI master and slave.

JtagProgramming

This is the example to explain "How to program a memory via JTAG?"

VLSITech_Study

AxiVIP

An AxiVIP supports both master and slave mode

FPGA_Starter

Xilinx FPGA Starter

Aes128_ECB_CBC_CFB_OFB_CTR

AES128 IP core supports ECB, CBC, CFB, OFB and CTR mode

DEScore

DES Encipher Decipher IP core

QuestaSimTutorial

Examples for performing the QuestaSim simulator on Windows

RegRTLGen

This is the open source tool which is used to create the System Verilog RTL code of register module

SynchronousFIFO

Synchronous FIFO with the configured parameters

Aes128

AES-128 cipher/encrypt and decipher/decrypt

BasicSynEnv

This is the basic synthesis environtment

crcCalculator

Synthesis RTL code of CRC calculator

FirstX2X

Simple AXI-to-AXI bridge

getPort

An example of Perl scritpt for referring

Python4RTLDesigner

The scripts are developed for RTL or logic designer.

SynchronousLIFO

Synchronous LIFO with the configured parameters

VG_Specification

All specifications of VG project