nexayq's starred repositories

barrier

Open-source KVM software

Language:CLicense:NOASSERTIONStargazers:26980Issues:261Issues:1514

FreeCAD

This is the official source code of FreeCAD, a free and opensource multiplatform 3D parametric modeler.

Language:C++License:NOASSERTIONStargazers:18586Issues:542Issues:4706

scapy

Scapy: the Python-based interactive packet manipulation program & library.

Language:PythonLicense:GPL-2.0Stargazers:10455Issues:235Issues:1606

iperf

iperf3: A TCP, UDP, and SCTP network bandwidth measurement tool

Language:CLicense:NOASSERTIONStargazers:6645Issues:230Issues:1072

pipreqs

pipreqs - Generate pip requirements.txt file based on imports of any project. Looking for maintainers to move this project forward.

Language:PythonLicense:Apache-2.0Stargazers:6040Issues:56Issues:275

Lemuroid

All in one emulator on Android!

Language:KotlinLicense:GPL-3.0Stargazers:2443Issues:43Issues:598

aves

Aves is a gallery and metadata explorer app, built for Android with Flutter.

Language:DartLicense:BSD-3-ClauseStargazers:2340Issues:28Issues:855

PacketSender

Network utility for sending / receiving TCP, UDP, SSL, HTTP

Language:C++License:GPL-2.0Stargazers:2324Issues:115Issues:243

icestudio

:snowflake: Visual editor for open FPGA boards

Language:JavaScriptLicense:GPL-2.0Stargazers:1684Issues:84Issues:434

hls4ml

Machine learning on FPGAs using HLS

Language:C++License:Apache-2.0Stargazers:1205Issues:56Issues:403

MGit

A Git client for Android.

Language:JavaLicense:GPL-3.0Stargazers:1192Issues:52Issues:539

warpinator

Share files across the LAN

Language:C++License:GPL-3.0Stargazers:1188Issues:27Issues:170

uip

The historical uIP sources

OpenFPGA

An Open-source FPGA IP Generator

Language:VerilogLicense:MITStargazers:795Issues:43Issues:438

vim-ai

AI-powered code assistant for Vim. OpenAI and ChatGPT plugin for Vim and Neovim.

Language:Vim ScriptLicense:MITStargazers:642Issues:12Issues:81

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Language:JavaScriptLicense:GPL-3.0Stargazers:530Issues:22Issues:434

agent

DWService agent for Linux, Mac and Windows

Language:PythonStargazers:424Issues:34Issues:0

CSI2Rx

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

Language:VHDLLicense:MITStargazers:369Issues:39Issues:6

bitfield

:cake: bit field diagram renderer

Language:JavaScriptLicense:MITStargazers:332Issues:10Issues:35

100DaysOfRTL

100 Days of RTL

Language:SystemVerilogStargazers:319Issues:26Issues:5

cocotbext-axi

AXI interface modules for Cocotb

Language:PythonLicense:MITStargazers:204Issues:13Issues:65

symbolator

HDL symbol generator

Language:PythonLicense:MITStargazers:177Issues:14Issues:15

python-obfuscator

I got tired of writing good code so I made good code to make bad code

Language:PythonLicense:MITStargazers:147Issues:3Issues:16

cocotbext-eth

Ethernet interface modules for Cocotb

Language:PythonLicense:MITStargazers:53Issues:8Issues:4

xilinx-coe-generator

Python script for generating Xilinx .coe files for RAM initializing

Language:PythonLicense:MITStargazers:14Issues:1Issues:0

axi-traffic-gen

File editor for the Xilinx AXI Traffic Generator IP

Language:PythonLicense:GPL-3.0Stargazers:14Issues:1Issues:2
Language:JavaScriptLicense:AGPL-3.0Stargazers:11Issues:8Issues:8

SPIControl

Tutorial

Language:VerilogStargazers:6Issues:2Issues:0

OpenFPGA

An Open-source FPGA IP Generator

Language:CLicense:MITStargazers:1Issues:1Issues:0