Neel Gala (neelgala)

neelgala

Geek Repo

Company:InCore Semiconductors Pvt. Ltd

Location:Chennai,India

Home Page:https://incoresemi.com

Github PK Tool:Github PK Tool

Neel Gala's repositories

ariane

Ariane is a 6-stage RISC-V CPU

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asciidoctor-lists

An asciidoctor extension that adds a list of figures, a list of tables, or a list of anything you want!

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asciidoctor-multipage

A configurable multipage HTML converter for Asciidoctor

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asciidoctor-skins

Control how your asciidoctor powered documentation looks

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asciidoctor-theme

Asciidoctor theme

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BluespecIntroGuide

An introductory guide to Bluespec (BSV)

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bsc-contrib

A place to share libraries and utilities that don't belong in the core bsc repo

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docs-dev-guide

Documentation developer guide

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Experimental_RISCV_Feature_Model

An experimental DSL to describe the full feature list of a RISC-V implementation, along with constraints on features and between features

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neorv32

:desktop_computer: An area-optimized, customizable MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

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openc906

OpenXuantie - OpenC906 Core

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openc910

OpenXuantie - OpenC910 Core

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opene902

OpenXuantie - OpenE902 Core

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opene906

OpenXuantie - OpenE906 Core

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riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

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riscv-config

RISC-V Configuration Validator

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riscv-crypto

RISC-V cryptography extensions standardisation work.

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riscv-elf-psabi-doc

A RISC-V ELF psABI Document

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riscv-isa-manual

RISC-V Instruction Set Manual

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riscv-isa-sim

Spike, a RISC-V ISA Simulator

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riscv-plic-spec

PLIC Specification

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riscv-v-spec

Working draft of the proposed RISC-V V vector extension

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rocket-chip

Rocket Chip Generator

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swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

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