mytoys's repositories
open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
adv_dbg_if
Advanced Debug Interface
Language:SystemVerilog000
Language:SystemVerilogNOASSERTION000
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Language:SystemVerilogNOASSERTION000
Language:SystemVerilogNOASSERTION000
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H264
H264视频解码verilog实现
Language:Verilog000
SSD-Tensorflow
Single Shot MultiBox Detector in TensorFlow
Language:Jupyter Notebook000