mytoys

mytoys's repositories

pulpino

An open-source microcontroller system based on RISC-V

Language:CNOASSERTION2 20

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Language:VerilogApache-2.01 10

adv_dbg_if

Advanced Debug Interface

Language:SystemVerilog000

apb2per

Language:SystemVerilog020

apb_event_unit

Language:SystemVerilogNOASSERTION020

apb_fll_if

Language:SystemVerilogNOASSERTION020

apb_gpio

Language:SystemVerilogNOASSERTION020

apb_i2c

Language:SystemVerilog020

apb_node

Language:SystemVerilog020

apb_pulpino

Language:SystemVerilogNOASSERTION000

apb_spi_master

Language:SystemVerilogNOASSERTION020

apb_timer

Language:SystemVerilogNOASSERTION000

apb_uart

Language:VHDL020

apb_uart_sv

Language:SystemVerilogNOASSERTION000

axi2apb

Language:SystemVerilogNOASSERTION000

axi_mem_if_DP

Language:SystemVerilogNOASSERTION000

axi_node

Language:SystemVerilogNOASSERTION020

axi_slice

Language:SystemVerilogNOASSERTION020

axi_slice_dc

Language:SystemVerilogNOASSERTION000

axi_spi_master

Language:SystemVerilogNOASSERTION020

axi_spi_slave

Language:SystemVerilogNOASSERTION020

core2axi

Core protocol to AXI bridge

Language:SystemVerilogNOASSERTION020

fpu

Language:SystemVerilogNOASSERTION020

H264

H264视频解码verilog实现

Language:Verilog000

IPApproX

Language:PythonBSD-3-Clause020

misclogic

Language:PythonMIT020

riscv

Language:SystemVerilogNOASSERTION020

rocket-chip-read

Language:Makefile020

SSD-Tensorflow

Single Shot MultiBox Detector in TensorFlow

Language:Jupyter Notebook000

zero-riscy

Language:SystemVerilogNOASSERTION020