anoop's repositories
chisel_axi
AXI Full Master and Slave interfaces with BRAM
awesome-machine-learning-in-compilers
Must read research papers and links to tools and datasets that are related to using machine learning for compilers and systems optimisation
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
black-parrot
A Linux-capable RISC-V multicore for and by the world
gem5
The official repository for the gem5 computer-system architecture simulator.
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
computer-engineering-resources
A curated list of Computer Engineering resources
gem5-resources
The official repository for the gem5 resources sources.
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
zynq-parrot
Dromajo Cosim