Lime-GPSDO FPGA gateware

This repository contains the FPGA gateware project for the Lime-GPSDO board.

The gateware can be built with the free version of the Altera Quartus tools.

Project is created with Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition. Although other Altera Quartus prime software versions supporting MAX10 family might work as well but it is recommended to use same version as project was created.

Branches

This repository contains the following branches:

master:
- Tested version of gateware.
develop:
- New features, modifications

Licensing

Please see the COPYING file(s). However, please note that the license terms stated do not extend to any files provided with the Altera design tools and see the relevant files for the associated terms and conditions.

About

Lime-GPSDO MAX10 Gateware

Languages

Language:Verilog 35.5%Language:C 23.5%Language:VHDL 17.2%Language:SystemVerilog 15.4%Language:Makefile 3.9%Language:Assembly 2.4%Language:Tcl 1.1%Language:C++ 0.7%Language:Stata 0.1%Language:GDB 0.1%Language:Shell 0.0%