Mukul Lokhande's repositories
aimet
AIMET is a library that provides advanced quantization and compression techniques for trained neural network models.
ApproximateMult
ILP-based Synthesized Approximate Multiplier
Cadence-RTL-to-GDSII-Flow
In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
DALI
A GPU-accelerated library containing highly optimized building blocks and an execution engine for data processing to accelerate deep learning training and inference applications.
deepmind-research
This repository contains implementations and illustrative code to accompany DeepMind publications
fixedpoint
Chisel Fixed-Point Arithmetic Library
gemmlowp
Low-precision matrix multiplication
ICC2_scripts
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
MAC
This project aims to create and deploy a 16-bit Multiply-Accumulate (MAC) unit that can handle two inputs. Each input comprises a single sign bit, three integer bits, and twelve fractional bits. The primary objective is to effectively accumulate the product of these inputs while preserving precision throughout the computational process
mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
MIT-6.5940
All Homeworks for TinyML and Efficient Deep Learning Computing 6.5940 • Fall • 2023 • https://efficientml.ai
once-for-all
[ICLR 2020] Once for All: Train One Network and Specialize it for Efficient Deployment
openhardwarelib
Verilog library for ASIC and FPGA designers
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
RISC-V-PathPlanner
Implementing a RISC-V CPU in Verilog that can run the Path Planning Algorithm
RTL-to-Gates-Synthesis-using-Synopsys-tools
For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, you will write an RTL model of a GCD circuit, synthesize and place and route the design, simulate at every stage, and analyze power.
SoomRV-Arty
SoomRV on the Arty A7 100T FPGA dev board
t81_558_deep_learning
T81-558: Keras - Applications of Deep Neural Networks @Washington University in St. Louis
torch-approx
GPU-accelerated Neural Network layers using Approximate Multiplications for PyTorch
transfomers-silicon-research
Research and Materials on Hardware implementation of Transformer Model
verilog-axi
Verilog AXI components for FPGA implementation
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro