Beast code in Giters

Mark Shaw's starred repositories

openssl

TLS/SSL and crypto library

Language:CApache-2.024988 1016 9736

An open source, portable, easy to use, readable and flexible TLS library, and reference implementation of the PSA Cryptography API. Releases are on a varying cadence, typically around 3 - 6 months between releases.

Language:CNOASSERTION5065 209 3840

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

Language:CNOASSERTION3292 142 1043

rocket-chip

Rocket Chip Generator

Language:ScalaNOASSERTION3096 196 954

verilator

Verilator open-source SystemVerilog simulator and lint system

Language:C++LGPL-3.02320 73 3346

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Language:AssemblyNOASSERTION2165 91 979

openocd

Official OpenOCD Read-Only Mirror (no pull requests)

Language:CNOASSERTION1565 480

neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Language:VHDLBSD-3-Clause1504 51 181

verilog-axi

Verilog AXI components for FPGA implementation

Language:VerilogMIT1363 52 67

pyOCD

Open source Python library for programming and debugging Arm Cortex-M microcontrollers

Language:PythonApache-2.01086 65 665

digilent-xdc

A collection of Master XDC files for Digilent FPGA and Zynq boards.

Language:TclMIT489 35 16

CMSIS_4

Cortex Microcontroller Software Interface Standard (V4 no longer maintained)

Language:C449 570

AMBA_AXI_AHB_APB

AMBA bus lecture material

Language:Verilog352 80

gen_amba_2021

AMBA bus generator including AXI4, AXI3, AHB, and APB

Language:CNOASSERTION147 3 4

High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS

This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.

Language:VHDL70 40