Michael Schaffner (msfschaffner)

msfschaffner

Geek Repo

Company:Google

Location:USA

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Michael Schaffner's starred repositories

opentitan

OpenTitan: Open source silicon root of trust

Language:SystemVerilogLicense:Apache-2.0Stargazers:2443Issues:105Issues:6541

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Language:SystemVerilogLicense:Apache-2.0Stargazers:1302Issues:96Issues:816

export_fig

A MATLAB toolbox for exporting publication quality figures

Language:MATLABLicense:BSD-3-ClauseStargazers:1254Issues:72Issues:380

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

openpiton

The OpenPiton Platform

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Language:SystemVerilogLicense:Apache-2.0Stargazers:401Issues:38Issues:58

vitetris

Classic multiplayer tetris for the terminal

Language:CLicense:BSD-2-ClauseStargazers:201Issues:9Issues:19

cva6-sdk

CVA6 SDK containing RISC-V tools and Buildroot

ariane

Ariane is a 6-stage RISC-V CPU

Language:SystemVerilogLicense:NOASSERTIONStargazers:1Issues:1Issues:0

edalize

An abstraction library for interfacing EDA tools

Language:PythonLicense:BSD-2-ClauseStargazers:1Issues:1Issues:0

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

Language:PythonLicense:GPL-3.0Stargazers:1Issues:1Issues:0

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

Language:SystemVerilogLicense:Apache-2.0Stargazers:1Issues:1Issues:0

openpiton

The OpenPiton Platform

Language:AssemblyStargazers:1Issues:2Issues:0

opentitan

OpenTitan: Open source silicon root of trust

Language:SystemVerilogLicense:Apache-2.0Stargazers:1Issues:1Issues:1

style-guides

lowRISC Style Guides

License:CC-BY-4.0Stargazers:1Issues:1Issues:0