mortbopet / Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

Home Page:https://ripes.me/

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Untangle ISA-specific information from the assembler framework.

mortbopet opened this issue · comments

Currently, defining an ISA and defining the assembler for said ISA is done in two different places, e.g.:

Ideally, all information regarding operations themselves - such as opcodes, fields, registers, etc.. would not be inherently tied to the assembler, but instead part of the ISA information. The assembler framework would then query the operations of a given instruction set, and generate the assembler based on said information. This is almost what's already done, but with the assembler being too strongly coupled with the instruction definitions.

If we manage to move instruction definitions to ISA files, meaning that the ISA files will contain all information about the ISA, we can start to query this more reliably in various different places in Ripes. One improvement that this refactor would allow is to avoid duplicating ISA information in the processor model decoders: https://github.com/mortbopet/Ripes/blob/master/src/processors/RISC-V/rv_decode.h - which instead should reference the ISA files.

Currrently, instructions are defined dynamically (e.g. https://github.com/mortbopet/Ripes/blob/master/src/assembler/rv_c_ext.h#L319C11-L323), meaning that all information that we specify when defining an instruction must lookup some runtime object to acquire the values of interest (opcode bitfields etc..). However, from the point of view of writing e.g. the RISC-V decoder model, we only need static information - hence there would be quite a bit of overhead in performing a bunch of dynamic, runtime lookups. As such, solving this issue should also consider whether there is a way to make instruction information (specifically bitfields) available at compile time.