Leo Moser's repositories
semicon2023-tgff
A Transmission-Gate D-FF (TGFF) for the Minimal Fab Design Contest
tt05-one-sprite-pony
This SVGA Verilog design has exactly one trick up its sleeve: it displays a sprite!
chip-gallery
This is the repository where I store the layout for chips that I have designed.
IIC-OSIC-TOOLS
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
leosoc-gfmpw-1
A simple dual-core SoC with true random number generators as payload.
cace
Circuit Automatic Characterization Engine
caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
FABulous
Fabric generator and CAD tools
globalfoundries-pdk-libs-gf180mcu_fd_pr
Primitives for GF180MCU provided by GlobalFoundries.
icps-tutorial
Schematic and layout for a NAND gate using the ICPS PDK
IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
iverilog
Icarus Verilog
open_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.
openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
OpenRAM
An open-source static random access memory (SRAM) compiler.
sky130_ef_ip__analog_switches
Set of analog switch circuits for general-purpose use
sky130_ef_ip__instramp
Instrumentation amplifier (analog IP example)
sky130_ef_ip__rdac3v_8bit
8-bit resistor ladder DAC with 3.3V output range
sky130_ef_ip__samplehold
Analog 3.3V sample and hold circuit, with buffered output
sky130_klayout_pdk
Skywaters 130nm Klayout PDK
tinytapeout_www
website source
tt-gds-action
Tiny Tapeout GDS Action (using OpenLane)
tt06-verilog-template
Submission template for Tiny Tapeout 06 - Verilog HDL Projects