Leo Moser (mole99)

mole99

Geek Repo

Location:Austria

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Leo Moser's repositories

tiny-vga

Tiny VGA Pmod board designed in KiCad

License:CC-BY-SA-4.0Stargazers:6Issues:1Issues:0

semicon2023-tgff

A Transmission-Gate D-FF (TGFF) for the Minimal Fab Design Contest

License:Apache-2.0Stargazers:5Issues:2Issues:0

tt05-one-sprite-pony

This SVGA Verilog design has exactly one trick up its sleeve: it displays a sprite!

Language:VerilogLicense:Apache-2.0Stargazers:5Issues:1Issues:0

qspi-pmod

A QSPI Pmod board designed in KiCad containing one Flash and two SPRAMs

License:Apache-2.0Stargazers:3Issues:0Issues:0

chip-gallery

This is the repository where I store the layout for chips that I have designed.

Language:PythonStargazers:2Issues:0Issues:0

ota-5t

A simple 5-transistor OTA.

Language:TclLicense:Apache-2.0Stargazers:2Issues:0Issues:0

IIC-OSIC-TOOLS

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Language:PythonLicense:Apache-2.0Stargazers:1Issues:0Issues:0

leosoc-gfmpw-1

A simple dual-core SoC with true random number generators as payload.

Language:VerilogLicense:Apache-2.0Stargazers:1Issues:1Issues:0
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cace

Circuit Automatic Characterization Engine

Language:PythonLicense:Apache-2.0Stargazers:0Issues:0Issues:0

caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

FABulous

Fabric generator and CAD tools

License:Apache-2.0Stargazers:0Issues:0Issues:0

globalfoundries-pdk-libs-gf180mcu_fd_pr

Primitives for GF180MCU provided by GlobalFoundries.

License:Apache-2.0Stargazers:0Issues:0Issues:0

gpi-test

This is a test of cocotbs GPI interface.

Language:CLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

icps-tutorial

Schematic and layout for a NAND gate using the ICPS PDK

License:Apache-2.0Stargazers:0Issues:0Issues:0

IHP-Open-PDK

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

License:Apache-2.0Stargazers:0Issues:0Issues:0

iverilog

Icarus Verilog

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open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

Language:PythonLicense:Apache-2.0Stargazers:0Issues:0Issues:0

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

Language:PythonLicense:Apache-2.0Stargazers:0Issues:0Issues:0

OpenRAM

An open-source static random access memory (SRAM) compiler.

Language:PythonLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

sky130_ef_ip__analog_switches

Set of analog switch circuits for general-purpose use

Language:ShellLicense:Apache-2.0Stargazers:0Issues:0Issues:0

sky130_ef_ip__instramp

Instrumentation amplifier (analog IP example)

License:Apache-2.0Stargazers:0Issues:0Issues:0

sky130_ef_ip__rdac3v_8bit

8-bit resistor ladder DAC with 3.3V output range

License:Apache-2.0Stargazers:0Issues:0Issues:0

sky130_ef_ip__samplehold

Analog 3.3V sample and hold circuit, with buffered output

License:Apache-2.0Stargazers:0Issues:0Issues:0

sky130_klayout_pdk

Skywaters 130nm Klayout PDK

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tinytapeout_www

website source

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tt-gds-action

Tiny Tapeout GDS Action (using OpenLane)

License:Apache-2.0Stargazers:0Issues:0Issues:0

tt06-verilog-template

Submission template for Tiny Tapeout 06 - Verilog HDL Projects

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