mohsaied

rtl2booksim

Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.

finn-hlslib

Vivado HLS library for FINN

github-markdown-toc

Easy TOC creation for GitHub README.md

hnocsim

lynx

mohsaied.github.io

A beautiful, simple, clean, and responsive Jekyll theme for academics

vision-transformers-cifar10

Let's train vision transformers (ViT) for cifar 10!

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research