mohamedhazem511

Certifications

N_BIT_GENERAL_PURPOSE_INTEGER_PROCESSOR_RISC_V

Graduation Project : Implement a 32-bit multi-Cycle microarchitecture RISC V processor based on Harvard Architecture on a FPGA kit(spartan-6) using Xilinx’s tool “ISE14.7”.

n_bits_comb_and_seq_binary_multipler

UART

verification_of_alu_using_SV

verification of alu using system verilog

async_fifo

An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO-buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain.

Automatic_Garage_Door_Controller

cache_system_integrate_with_risc_v

Cache Controller Implementation with Write-Through Policy & integrate with single cycle RISC-V

clk_div

counter

Linear_Feedback_Shift_Register

mohamedhazem511

n_bit_ring_counter

N-bit ring counter using generate statements (for generate).

pipelined-rsic_v

single-cycle_risc-v