mohamedamine99 / Digital-Lock-with-VHDL-state-machine

Digital-Lock-with-VHDL-state-machine

Table of Contents

1. About The Project
2. How it works
3. Software Requirements
4. Software implementation
• Behavioral module
• Testbench
5. Results
6. Conclusion
7. Contact

About the project

This project is about creating a VHDL module and a test bench for a digital lock with state machine. The lock's features include :

• Password verification
• Password modification
• Alarm system

How it works:

-The Lock Code is a 4-digit number
-The user enters a combination on the keyboard of the device and presses the "Validate" key

• If the code entered is true the lock will wait until the user releases the "Validate" button to open. * The lock remains open for a few seconds before closing automatically * If the code is not the one registered, the lock will not open. * If the code is entered 3 times and is wrong then an alarm signal goes off and does not stop until a true code is entered
  • The user has the possibility to change his password:
    • He presses the “conf” button then must enter the previous code correctly then presses the validate button.
    • If the code entered is correct, the user then enters the new code and presses the validate button to confirm. So the code is changed

the keypad:

• Each button is represented by a code of two vectors of 4 bits. the vectors represent the row and column of each button.

Software Requirements:

Xilinx ISE suite 14.7 (or higher)

Software implementation:

Behavioral module:

• You can find the well commented behavioral module here

Testbench:

• You can find the Testbench here

Results:

Now let's check our simulation results:

let's go to the explanation :

The user pushed the configuration button to enter the password configuration mode .

Now the user types the previous password , for security check, by pushing consecutively 4 buttons on the keyPad .

Now the user Presses the validate button to confirm the password .

All is set now the user types the new password then he confirms by pushing the validate button.

Now we test our new password to check whether it changed successfully or not .

password is correct ! All is in order, The door opens and remains so , for some 13 seconds.

Now let's type a wrong password : nothing happens and the door remains closed.

Now let's type a wrong password for the 2nd time : nothing happens and the door remains closed.

Now let's type a wrong password for the 3rd time.

After the 3rd unsuccessfull attempt at typing the correct password , an alarm is triggered and keeps working until the correct password is entered and doors reopens for 13 seconds

Conclusion:

In this project, we successfullty implemented a VHDL solution for digital Lock with proper functionning and multiple features including : password modification and an alarm system, using a state machine algorithm . This solution can further implemented on a hardware level.

Contact:

• Mail : [e-mail] -- [e-mail]
• Linked-in profile: https://www.linkedin.com/in/mohamed-amine-ben-abdeljelil-86a41a1a9/