mitoksim

wb2axi

Wishbone to ARM AMBA 4 AXI

riscv-ca-teaching

RISC-V in Practical Computer Architecture Education

riscv-cocotb

cocotb infrastructure for RISC-V core testing

hdmi-boost

Small board which adds HDMI amplifiers to one TX+RX ports -- mainly for usage with the Numato Opsis board

uartdpi

UART DPI module

darpa-idea

DARPA IDEA program

verilog

core_usb_cdc

Basic USB-CDC device core (Verilog)

Cores-SweRV-EL2

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openlane-examples

Examples from the Openlane repository, adapted as Fusesoc cores

riscv

serv

SERV - The SErial RISC-V CPU

HDMI2USB-firmware-prebuilt

Prebuilt firmware for the HDMI2USB device (and the Digilent Atlys board) and OS drivers.

HDMI2USB-mode-switch

Tool for switching boards supported by HDMI2USB firmware between multiple different modes (programming, webcam, etc).

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

verilog

wb2axi

Wishbone to ARM AMBA 4 AXI

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

educational-materials

Educational materials for RISC-V

fusesoc_cores

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

opensource-design-verification-workshop

Open Source Design Verification Workshop

opentitan

OpenTitan: Open source silicon root of trust

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

riscv-boom

BOOM: Berkeley Out-of-Order Machine

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

subservient

Small SERV-based SoC primarily for OpenMPW tapeout

swerv_eh1-1

A directory of Western Digital’s RISC-V SweRV Cores

verilator

Verilator open-source SystemVerilog simulator and lint system