minseongg

antlr4rust

ANTLR4 parser generator runtime for Rust programming laguage

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

corundum

Open source, high performance, FPGA-based NIC

cs420

KAIST CS420: Compiler Design (2020 Spring)

digraph

dynamatic

From C/C++ to Dynamically-Scheduled Circuits

firrtl

Flexible Intermediate Representation for RTL

firrtl-to-verilog

FIRRTL to Verilog translator

FPU

IEEE 754 floating point unit in Verilog

infra-public

kaist-cp.github.io

linked-hash-map

A HashMap wrapper that holds key-value pairs in insertion order

michaeljclark.github.io

RISC-V simulator for x86-64

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-elf-psabi-doc

A RISC-V ELF psABI Document

rocket-chip

Rocket Chip Generator

sv-parser

SystemVerilog parser library fully complient with IEEE 1800-2017

tuple-utils

cs220

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

fpga_readings

Recipe for FPGA cooking

riscv-boom-read

riscv-sodor

educational microarchitectures for risc-v isa

shakeflow

ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators (ASPLOS 2023)

typenum

Compile time numbers in Rust.