minecraftdixit

Digital-ASIC-LAB

Verilog Codes for various Design

Gmake

Gui Based Make file generator

spi-

Serial peripheral interface protocol using verilog and testbench

adruino_extract

Bash script for adruino uno based microcontroller firmware extraction

AES

128 bit aes implementation

Baremetal-Arm-programming

Baremetal using KEIL U VISION for STM32F412ZGT6

chisel

Chisel: A Modern Hardware Design Language

CNN_fpga-

CNN on fpga using verilog

DPU

fifo-

synchronous fifo verification using system verilog

snakerobot

Snake Robot using Adruino mega , IR sensor , ESP 32 CAM

Hardware_Codesign_lab

hardware software codesign

Hardware_for_ai

hardware for ai

Hls-BRAM-Integration-

Bram HLS

HLS-codes

HLS codes for rtl generation

litex

Build your hardware, easily!

minecraftdixit

Config files for my GitHub profile.

NAS

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

protocols

pynqZ2-whl

riscv_embedded

RTC-

To make Real Time Clock using verilog

sequence-detector

Mealy Machine Based Sequence Detector

system-verilog-

sv practice codes

uart-using-verilog

uart implementation using verilog with testbench

uart_axi

vivado implementation of axi uart on fpga

verilog-codes-

mini projects

videofy

react based platform

ZCU