avisekh007 (midn8hustlr)

midn8hustlr

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Location:Bharat

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avisekh007's repositories

MSI_cache_coherence

Implementing a snoopy cache coherence for dual core processor with MSI protocol using Verilog HDL

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booth-multiplier-bist

4-bit Booth's Multiplier circuit with Built-in Self-test feature

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deeplearning.ai-notes

These are my personal notes which I prepared during deep learning specialization taught by AI guru Andrew NG. I have used diagrams and code snippets from the code whenever needed but following The Honor Code.

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DeepLearning.ai-Summary

This repository contains my personal notes and summaries on DeepLearning.ai specialization courses. I've enjoyed every little bit of the course hope you enjoy my notes too.

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tmux-material

Material You theme for tmux

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Deep-Neural-Network-Hardware-Accelerator

SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software

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dotfiles-hyprland

My personal dotfiles based on hyprland and ags.

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dots-hyprland-end4

For contributing to end4's dots

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dots-hyprland-wiki

contributing fork

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Hardware-CNN

A convolutional neural network implemented in hardware (verilog)

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MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

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Online-Face-Recognition-and-Authentication

Hsin-Rung Chou, Jia-Hong Lee, Yi-Ming Chan, and Chu-Song Chen, "Data-specific Adaptive Threshold for Face Recognition and Authentication," IEEE International Conference on Multimedia Information Processing and Retrieval, MIPR 2019

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tiny-tpu

Small-scale Tensor Processing Unit built on an FPGA

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VerilogBoy

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

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zoomme

Application for zooming and noting desktop ('ZoomIt!' Linux analog).

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