Beast code in Giters

michg's repositories

Python script for controlling the debug-jtag port of riscv cores

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c compiler beluga with riscv32 backend

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assembler and linker for riscv32

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CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc

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C11 compiler (mirror)

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graph based intermediate representation and backend for optimising compilers

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Another simulation backend for nmigen using yosys

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A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

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