Michael O'Dea's repositories

CS100

CS100

Stargazers:0Issues:2Issues:0
Language:GDBStargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0
Language:CStargazers:0Issues:0Issues:0
Language:CStargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0
Language:CStargazers:0Issues:0Issues:0
Language:CStargazers:0Issues:0Issues:0

CS120BLabs

Labs written in C

Language:CStargazers:0Issues:0Issues:0
Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0
Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0
Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0

CS168VLSI

Various labs that I used Verilog for circuit analysis and top down/bottom up designs

Stargazers:0Issues:0Issues:0

cs170project1

8-Puzzle Project

Language:C++Stargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

projects

school projects

Stargazers:0Issues:0Issues:0

Senior_Design_Technical_Report

A technical documentation describing the work my team and I did for our project.

Stargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0
Language:HTMLStargazers:0Issues:1Issues:0