miaochenlu / MCPU

tomasulo algorithm / cache / pipeline cpu / single cycle cpu

MCPU

tomasulo algorithm / cache / pipeline cpu / single cycle cpu (RISC-V)

Todo

• Basic Tomasulo
• Branch Prediction
• Exception Handling
• DCache & ICache

References:

• https://github.com/XOR-op/TransistorU
• https://github.com/ridecore/ridecore
• https://github.com/dreamATD/TomRiVer-CPU