Jiuxi Meng (mengjiuxi)

mengjiuxi

Geek Repo

Location:London

Home Page:jiuximeng.com

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Jiuxi Meng's repositories

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FPGA_project

This is a playground for verilog

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SVNES

NES implementation using SystemVerilog (under development)

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scikit-learn

scikit-learn: machine learning in Python

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Vitis-Tutorials

Vitis In-Depth Tutorials

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Y1Labs

Soton Electronic Engineering Year1 (2013-2014) Labs

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