Jatinder Singh's repositories
100daysofrtl
#100daysofrtl
ICS-OT_SIG
A repository dedicated to the activity of the CWE-CAPEC ICS/OT Special Interest Group.
XilinxTclStore
Xilinx Tcl Store
behavioral-model
Rewrite of the behavioral model as a C++ project without auto-generated code (except for the PD interface)
chisel3
Chisel 3
docs
TensorFlow documentation
EloquentArduino
IO, scheduling, utils, machine learning... for Arduino
hw-cwe-sig
GitHub Repository for the HW CWE SIG
MACS
MACS -- Model-based Analysis of ChIP-Seq
meta-xilinx
Xilinx device and board support for Yocto/OE-core.
mqttlog
A logging backend for "github.com/op/go-logging" to send messages to one or more MQTT topics
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
owasp.github.io
OWASP Foundation main site repository
PI
P4Runtime - a control plane framework and tools for the P4 programming language
PLC_Programming
Rockwell Automation RSLogix 500 Programs
risc-v-core
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard
riscv-trace-spec
Working Draft of the RISC-V Processor Trace Specification
skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
tutorials
P4 language tutorials
u-boot-xlnx
The official Xilinx u-boot repository
yowsup
The python WhatsApp library