masoud-ata / AssembleRisc

A Python assembler for RISC-V

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AssembleRisc

A Python assembler for RISC-V with support for RV32IMFAC extensions

Requirements

The assembler has been tested using Python 3.6 on both Linux and windows. It uses the ply package (Python Lex-Yacc), which is listed in the requirements.txt file, and therefore can be installed with the following command:

pip install -r requirements.txt

How to run

First, cd to the src directory. By default, the assembler takes the examples\tryouts.s as input and can be invoked like:

$ python main.py

If you want to use another file as input, then you can run the main.py file with your input assembly file (here assumed to be named my_asm.s and in the same src directory):

$ python main.py -i my_asm.s

The output files, both in textual binary and hexadeciaml, are placed in the output directory.

Supported instructions

RV32I

Instruction Format Supported Instruction Format Supported
add R sb S
sub R sh S
sll R sw S
slt R beq B
sltu R bne B
xor R blt B
srl R bge B
sra R bltu B
or R bgeu B
and R lui U
addi I auipc U
slti I jal J
sltiu I jalr J
xori I fence I
ori I fence.i I
andi I ecall I
slli I ebreak I
srli I csrrw I
srai I csrrs I
lb I csrrc I
lh I csrrwi I
lw I csrrsi I
lbu I csrrci I
lhu I

RV32C

Instruction Format Supported Instruction Format Supported
c.and CA c.srai CB
c.or CA c.andi CB
c.xor CA c.add CR
c.sub CA c.mv CR
c.lw CL c.j CJ
c.sw CS c.jal CJ
c.beqz CB c.jr CR
c.bneq CB c.jalr CR
c.li CI c.nop CI
c.lui CI c.addi16sp CI
c.addi CI c.addi4spn CIW
c.slli CI c.fld CL
c.srli CB c.flw CL
c.slli64 CI c.fsd CS
c.fldsp CI c.fsw CS
c.lwsp CI c.ebreak CI
c.flwsp CI
c.fsdsp CSS
c.swsp CSS
c.fswsp CSS

RV32M

Instruction Format Supported Instruction Format Supported
mul R div R
mulh R divu R
mulhsu R rem R
mulhu R remu R

RV32F

Instruction Format Supported Instruction Format Supported
fadd.s R feq.s R
fsub.s R flt.s R
fmul.s R fle.s R
fdiv.s R fsqrt.s R
fmv.x.w R flw I
fmv.w.x R fsw S
fsgnj.s R fcvt.s.w R
fsgnjn.s R fcvt.s.wu R
fsgnjx.s R fclass.s R
fmin.s R fmadd.s R4
fmax.s R fmsub.s R4
fcvt.w.s R fnmsub.s R4
fcvt.wu.s R fnmadd.s R4

RV32A

Instruction Format Supported Instruction Format Supported
lr.w R amoor.w R
sc.w R amomin.w R
amoswap.w R amomax.w R
amoadd.w R amominu.w R
amoxor.w R amomaxu.w R
amoand.w R

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A Python assembler for RISC-V

License:Apache License 2.0


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